COMPUTER ARCHITECTURE (Major) MAKAUT BCA SECOND SEM

Module 1: Data Representation

1.1.

Data Representation

13

1.2.

Number Systems

14

1.2.1.

Introduction

14

1.2.2.

Types of Number Systems

15

1.2.2.1.

Binary Number System

15

1.2.2.2.

Decimal Number System

16

1.2.2.3.

Octal Number System

16

1.2.2.4.

Hexadecimal Number System

16

1.2.2.5.

Relationship between Binary, Octal and Hexadecimal Number Systems

17

1.3.

Alphanumerical Representation

17

1.3.1.

EBCDIC

18

1.3.2.

ASCII Code

19

1.3.3.

Unicode

20

1.4.

Complements

21

1.4.1.

1’s Complement

21

1.4.2.

2’s Complement

22

1.4.3.

9’s Complement

24

1.4.4.

10’s Complement

25

1.4.5.

(r - 1)’s Complement

26

1.4.6.

r’s Complement

28

1.5.

Fixed Point Representation

28

1.5.1.

Integer Representation

29

1.5.2.

Arithmetic Addition and Subtraction

30

1.5.3.

Overflow

31

1.5.4.

Decimal Fixed Point Representation

33

1.6.

Floating Point Representation

33

1.7.

IEEE 754 Floating Point Representation

35

1.8.

Exercise

37

Module 2: Computer Arithmetic

2.1.

Computer Arithmetic

37

2.1.1.

Introduction

37

2.1.2.

Addition and Subtraction Algorithm

37

2.1.2.1.

Addition and Subtraction of Signed-Magnitude Data

38

2.1.2.2.

Addition and Subtraction Using Signed 2’s Complement Data

39

2.1.3.

Multiplication Algorithm

45

2.1.3.1.

Booth’s Algorithm

45

2.1.3.2.

Steps of Booth Algorithm: Multiplication of Two 4-Bit Binary Numbers

45

2.1.4.

Division Algorithm

48

2.1.4.1.

Restoring Division

49

2.1.4.2.

Non-Restoring Division

51

2.2.

Exercise

53

Module 3: Register Transfer and Micro-Operations

3.1.

Register Transfer Language (RTL)

54

3.1.1.

Introduction

54

3.1.2.

Register Transfer

55

3.1.2.1.

Bus Transfer/Bus System for Registers

55

3.1.2.2.

Memory Transfers-Memory Read, Memory Write

56

3.1.3.

Micro-Operations

56

3.1.3.1.

Arithmetic Micro-Operations

57

3.1.3.2.

Logic Micro-Operation

59

3.1.3.3.

Shift Micro-Operations

61

3.1.4.

Binary Adder

63

3.1.5.

Binary Adder-Subtractor

64

3.1.6.

Binary Incrementer

64

3.1.7.

Arithmetic Circuit for Arithmetic Micro Operations

65

3.1.8.

One State Logic Circuit

67

3.1.8.1.

Selective Set Operation

68

3.1.8.2.

Selective Complement Operation

68

3.1.8.3.

Selective Clear Operation

68

3.1.8.4.

Mask Operation

68

3.1.8.5.

Insert Operation

69

3.1.8.6.

Clear Operation

69

3.2.

Exercise

70

Module 4: Basic Computer Organization and Design

4.1.

Basic Computer Organisation and Design

71

4.1.1.

Introduction

71

4.1.2.

Basic Components of Computer Organisation

71

4.1.3.

Common Bus System

73

4.1.4.

Timing and Control

74

4.2.

Register

75

4.2.1.

Introduction

75

4.2.2.

List of Basic Computer Registers

75

4.3.

Instructions Codes

77

4.3.1.

Introduction

77

4.3.2.

Stored Program Organization

77

4.3.3.

Addressing Modes

78

4.3.3.1.

Immediate Addressing

79

4.3.3.2.

Direct (or Absolute) Address

79

4.3.3.3.

Indirect Address

80

4.3.3.4.

Displacement Addressing/Effective Address

80

4.4.

Computer Instructions

82

4.4.1.

Memory Reference Instructions

82

4.4.2.

Register-Reference Instructions

84

4.4.3.

Input-Output Instructions

85

4.5.

Instruction Cycle

85

4.6.

Control Unit

88

4.6.1.

Introduction

88

4.6.2.

Functions of Control Unit

88

4.6.3.

Block Diagram of Control Unit

88

4.6.4.

Control Design Techniques

89

4.7.

Exercise

91

Module 5: Microprogrammed Control

5.1.

Micro-Programmed Control

92

5.1.1.

Introduction

92

5.1.2.

Microinstruction

92

5.1.3.

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COMPUTER ARCHITECTURE (Major) MAKAUT BCA SECOND SEM

AUTHORS: Subhrajit  Chakraborty 

ISBN  : 978-93-5755-497-8

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