• Out-of-Stock
Computer System Architecture 2 semester second semester
search
  • Computer System Architecture 2 semester second semester
  • Computer System Architecture 2 semester second semester

Computer System Architecture

₹120.00
Tax excluded

Shiv Kumar Modgil & Ranbir Kaur Mann

ISBN - 9789351638483

Quantity

Punjab Technical University PTU BCA, Second Semester
Syllabus
 
(BSBC 204) COMPUTER SYSTEM ARCHITECTURE
 
SECTION-A
Introduction to Computer Organization: Introduction to Computer and CPU (Computer Organization, Computer Design and Computer Architecture), Stored Program Concept- Von Neumann Architecture. Introduction to Flynn’s Classification- SISD, SIMD, MIMD.
Register Transfer and Micro Operations: Introduction to Registers, Register Transfer Language, Data Movement among Registers and Memory.
Micro Operations: Introduction to Micro Operations, Types of Micro Operations-Logic Operations, Shift Operations, Arithmetic and Shift Operations.
Common Bus System: Introduction to Common Bus System, Types of Buses (Data Bus, Control Bus, Address Bus), 16 Bit Common Bus System-Data Movement among Registers using Bus.                                                                         (09)
 
SECTION-B
Basic Computer Instructions: Introduction to Instruction, Types of Instructions (Memory Reference, I/O Reference and Register Reference), Instruction Cycle, Instruction Formats (Direct and Indirect Address Instructions, Zero Address, One Address, Two Address and Three Address Instructions).
Interrupt: Introduction to Interrupt and Interrupt Cycle.
Design of Control Unit: Introduction to Control Unit, Types of Control Unit (Hardwired & Micro Programmed Control Unit).
Addressing Modes: Introduction & Different Types of Addressing Modes.               (09)
 
SECTION-C
I/O Organization: I/O Interface Unit, Types of Ports (I/O port, Network Port, USB Port, Serial and Parallel Port), Concept of I/O Bus, Isolated I/O versus Memory Mapped I/O.
I/O Data Transfer Techniques: Programmed I/O, Interrupt Initiated I/O, DMA Controller and IOP.
Synchronous and Asynchronous Data Transfer: Concept of Strobe and Handshaking, Source and Destination Initiated Data Transfer.       (09)
 
SECTION-D
Stack Organization: Memory Stack and Register Stack.
Memory Organization: Memory Hierarchy, Main Memory (RAM and ROM Chips, Logical and Physical Addresses, Memory Address Map, Memory Connection to CPU), Associative Memory.
Cache Memory: Cache Memory (Initialization of Cache Memory, Writing Data into Cache, Locality of Reference, Hit Ratio), Replacement Algorithms (LRU and FIFO).
Cache Memory Mapping Techniques: Direct Mapping, Associative Mapping and Set- Associative Mapping. Harvard Architecture, Mobile Devices Architecture (Android, Symbian and Windows Lite), Layered Approach Architecture. (09)
PTU2016/BCA/2/04

Specific References

EAN13
9789351638483
New
Comments (0)
No customer reviews for the moment.